In a typical system, an integrated circuit, memory devices, and other electronic components are mounted on a printed circuit board. The integrated circuit includes memory interface circuitry that is used to relay data back and forth between the integrated circuit and the memory devices (i.e., the memory interface circuitry is used to read data from and write data into the memory devices).
In general, the memory interface circuitry can be implemented as either an “in-order” or an “out-of-order” memory controller. In-order memory controllers process memory access requests in order and offer determinism on memory scheduling but often lack scheduling efficiency in terms of memory bandwidth utilization. Out-of-order memory controllers can process access requests out of order and can offer improved memory bandwidth utilization but the scheduling is non-deterministic.
Certain systems may, however, include a mixture of different types of clients on an integrated circuit. For example, the integrated circuit may include a first portion of clients which are capable of out-of-order data return and a second portion of clients which can only handle in-order data return. In such types of systems, the memory controller will always need to reorder the data before returning it to satisfy the needs of the in-order clients. By always performing data reordering at the memory controller, the improved efficiency of out-of-order clients is effectively eliminated due to the presence of the in-order clients. This results in an inefficient memory system with sub-optimal latency, higher power consumption, and increased cost due to circuitry that is needed to support data reordering for each and every client at the memory controller.
It is within this context that the embodiments described herein arise.